178 lines
6.0 KiB
Python
178 lines
6.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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#
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# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2024 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("F5"), IOStandard("LVCMOS33")),
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("clk50", 0, Pins("D4"), IOStandard("LVCMOS33")),
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# DDR3L
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("ddram", 0,
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Subsignal("a", Pins(
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"F12 D15 J15 E16 G11 F15 H13 G15",
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"H12 H16 H11 H14 E12 G16 J16"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("E15 D11 F13"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("D14"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("E13"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("G12"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("A13 D9"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"A14 C12 B14 D13 B16 C11 C16 C14",
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"A9 B10 C8 B12 A8 A12 C9 B11"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_60")),
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Subsignal("dqs_p", Pins("B15 B9"), IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_60")),
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Subsignal("dqs_n", Pins("A15 A10"), IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_60")),
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Subsignal("clk_p", Pins("G14"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("F14"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("E11"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("D16"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("M16"), IOStandard("LVCMOS33")),
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),
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# Differential Data Multiple Interface
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("ddmi", 0,
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Subsignal("clk_p", Pins("C1"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("B1"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("E2"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("D1"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("F2"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("E1"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("G2"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("G1"), IOStandard("TMDS_33"))
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),
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# USB-C
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("usb", 0,
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Subsignal("d_p", Pins("B2")),
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Subsignal("d_n", Pins("A2")),
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Subsignal("pullup", Pins("C2")),
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IOStandard("LVCMOS33")
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),
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# DUAL USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("H2 K1")),
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Subsignal("dm", Pins("H1 J1")),
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IOStandard("LVCMOS33")
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),
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# ETHERNET
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("eth", 0,
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Subsignal("rx_data", Pins("F3 F4"), Misc("PULLUP")),
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Subsignal("tx_data", Pins("D3 E3")),
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Subsignal("tx_en", Pins("G4")),
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Subsignal("crs_dv", Pins("H3"), Misc("PULLUP")),
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Subsignal("rst_n", Pins("H4")),
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IOStandard("LVCMOS33")
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),
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# LVDS
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("ds", 0,
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Subsignal("ds0", Pins("M2")),
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Subsignal("ds1", Pins("R2")),
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Subsignal("ds2", Pins("T4")),
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IOStandard("LVDS_25")
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),
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# DEBUG UART
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("serial", 0,
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Subsignal("tx", Pins("L2")),
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Subsignal("rx", Pins("L3")),
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IOStandard("LVCMOS33")
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),
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# MMOD
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("L12")),
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#Subsignal("clk", Pins("")), # Accessed through STARTUPE2
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Subsignal("dq", Pins("J13 J14 K15 K16")),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SD-mode interface
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("sdcard", 0,
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Subsignal("cd", Pins("K3")),
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Subsignal("clk", Pins("R6")),
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Subsignal("cmd", Pins("T8")),
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Subsignal("data", Pins("T7 P8 T9 T5")),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SPI interface
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("spisdcard", 0,
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Subsignal("clk", Pins("R6")),
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Subsignal("mosi", Pins("T8")),
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Subsignal("cs_n", Pins("T5")),
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Subsignal("miso", Pins("T7")),
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IOStandard("LVCMOS33"),
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),
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]
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_io_v0 = [
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v0", variant="a7-35", toolchain="vivado"):
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assert revision in ["v0"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v0":
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io += _io_v0
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device = {
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"a7-35": "xc7a35tftg256-1"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]"
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix1 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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