91 lines
3.2 KiB
Python
Executable File
91 lines
3.2 KiB
Python
Executable File
#!/usr/bin/env python3
|
||
|
||
#
|
||
# This file is part of LiteX-Boards.
|
||
#
|
||
# Copyright (c) 2024 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
|
||
# SPDX-License-Identifier: BSD-2-Clause
|
||
|
||
# Build/use
|
||
# Build/Load bitstream:
|
||
# ./xilinx_zc706.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load
|
||
#
|
||
# litex_server --jtag --jtag-config openocd_xc7z_smt2-nc.cfg
|
||
#
|
||
# In a second terminal:
|
||
# litex_cli --regs # to dump all registers
|
||
# Or
|
||
# litex_term crossover # to have access to LiteX bios
|
||
#
|
||
# --------------------------------------------------------------------------------------------------
|
||
|
||
from migen import *
|
||
|
||
from litex.gen import *
|
||
|
||
from litex_boards.platforms import xilinx_zc706
|
||
|
||
from litex.soc.cores.clock import *
|
||
from litex.soc.integration.soc_core import *
|
||
from litex.soc.integration.builder import *
|
||
from litex.soc.cores.led import LedChaser
|
||
|
||
# CRG ----------------------------------------------------------------------------------------------
|
||
|
||
class _CRG(LiteXModule):
|
||
def __init__(self, platform, sys_clk_freq):
|
||
self.rst = Signal()
|
||
self.cd_sys = ClockDomain()
|
||
|
||
# # #
|
||
|
||
# Clk/Rst.
|
||
clk200 = platform.request("clk200")
|
||
|
||
# PLL.
|
||
self.pll = pll = S7PLL(speedgrade=-1)
|
||
self.comb += pll.reset.eq(self.rst)
|
||
pll.register_clkin(clk200, 200e6)
|
||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
||
|
||
# BaseSoC ------------------------------------------------------------------------------------------
|
||
|
||
class BaseSoC(SoCCore):
|
||
def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
|
||
platform = xilinx_zc706.Platform()
|
||
kwargs["uart_name"] = "crossover"
|
||
kwargs["with_jtagbone"] = True
|
||
|
||
# CRG --------------------------------------------------------------------------------------
|
||
self.crg = _CRG(platform, sys_clk_freq)
|
||
|
||
# SoCCore ----------------------------------------------------------------------------------
|
||
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs)
|
||
|
||
# Leds -------------------------------------------------------------------------------------
|
||
if with_led_chaser:
|
||
self.leds = LedChaser(
|
||
pads = platform.request_all("user_led"),
|
||
sys_clk_freq = sys_clk_freq
|
||
)
|
||
|
||
# Build --------------------------------------------------------------------------------------------
|
||
def main():
|
||
from litex.build.parser import LiteXArgumentParser
|
||
parser = LiteXArgumentParser(platform=xilinx_zc706.Platform, description="LiteX SoC on ZC706.")
|
||
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
|
||
args = parser.parse_args()
|
||
|
||
soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict)
|
||
builder = Builder(soc, **parser.builder_argdict)
|
||
if args.build:
|
||
builder.build(**parser.toolchain_argdict)
|
||
|
||
if args.load:
|
||
prog = soc.platform.create_programmer()
|
||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||
|
||
if __name__ == "__main__":
|
||
main()
|