2012-01-09 10:28:48 -05:00
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from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.corelogic.fsm import FSM
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s = Signal()
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2012-02-14 07:12:43 -05:00
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myfsm = FSM("FOO", "BAR")
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2012-01-09 10:28:48 -05:00
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myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR))
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myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO))
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print(verilog.convert(myfsm.get_fragment(), {s}))
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