40 lines
1.1 KiB
Python
40 lines
1.1 KiB
Python
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC, IntegratedBIOS
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class _CRG(Module):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class SimpleSoC(GenSoC, IntegratedBIOS):
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default_platform = "de0nano" # /!\ Adapt this!
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clk_name = "clk50" # /!\ Adapt this!
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clk_freq = 50*1000000 # /!\ Adapt this!
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def __init__(self, platform):
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GenSoC.__init__(self, platform,
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clk_freq=self.clk_freq,
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cpu_reset_address=0)
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IntegratedBIOS.__init__(self)
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self.submodules.crg = _CRG(platform.request(self.clk_name))
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# use on-board SRAM as SDRAM
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sys_ram_size = 16*1024
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self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
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self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
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self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
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default_subtarget = SimpleSoC
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