2013-02-22 17:19:37 -05:00
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from migen.genlib.complex import *
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2013-01-05 08:18:36 -05:00
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from migen.fhdl import verilog
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w = Complex(32, 42)
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A = SignalC(16)
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B = SignalC(16)
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Bw = SignalC(16, variable=True)
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C = SignalC(16)
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D = SignalC(16)
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sync = [
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Bw.eq(B*w),
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C.eq(A + Bw),
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D.eq(A - Bw)
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]
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print(verilog.convert(Fragment(sync=sync)))
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