129 lines
2.7 KiB
Python
129 lines
2.7 KiB
Python
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from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.flow.actor import Sink, Source
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from migen.bank.description import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoclib.ethmac.common import *
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class MIIPHYTX(Module):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_description(8))
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###
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tx_en_r = Signal()
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tx_data_r = Signal(4)
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self.sync += [
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pads.tx_er.eq(0),
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pads.tx_en.eq(tx_en_r),
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pads.tx_data.eq(tx_data_r),
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("SEND_LO")
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)
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)
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fsm.act("SEND_LO",
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tx_data_r.eq(sink.d[0:4]),
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tx_en_r.eq(1),
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NextState("SEND_HI")
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)
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fsm.act("SEND_HI",
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tx_data_r.eq(sink.d[4:8]),
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tx_en_r.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.eop,
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NextState("IDLE")
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).Else(
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NextState("SEND_LO")
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)
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)
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class MIIPHYRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_description(8))
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###
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sop = source.sop
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set_sop = Signal()
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clr_sop = Signal()
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self.sync += \
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If(clr_sop,
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sop.eq(0)
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).Elif(set_sop,
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sop.eq(1)
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)
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lo = Signal(4)
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hi = Signal(4)
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load_nibble = Signal(2)
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self.sync += \
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If(load_nibble[0],
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lo.eq(pads.rx_data)
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).Elif(load_nibble[1],
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hi.eq(pads.rx_data)
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)
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self.comb += [
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source.d.eq(Cat(lo, hi))
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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set_sop.eq(1),
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If(pads.dv,
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load_nibble.eq(0b01),
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NextState("LOAD_HI")
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)
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)
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fsm.act("LOAD_LO",
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source.stb.eq(1),
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If(pads.dv,
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clr_sop.eq(1),
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load_nibble.eq(0b01),
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NextState("LOAD_HI")
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).Else(
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source.eop.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("LOAD_HI",
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load_nibble.eq(0b10),
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NextState("LOAD_LO")
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)
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class MIIPHYCRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads):
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self._reset = CSRStorage()
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###
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self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
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self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class MIIPHY(Module, AutoCSR):
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def __init__(self, clock_pads, pads):
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self.dw = 8
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self.submodules.crg = MIIPHYCRG(clock_pads, pads)
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self.submodules.tx = RenameClockDomains(MIIPHYTX(pads), "eth_tx")
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self.submodules.rx = RenameClockDomains(MIIPHYRX(pads), "eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source
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