litex/migen/bus/csr.py

from migen.fhdl.structure import *
from migen.bus.simple import *

_desc = Description(
	(M_TO_S,	"adr",		14),
	(M_TO_S,	"we",		1),
	(M_TO_S,	"dat_w",	8),
	(S_TO_M,	"dat_r",	8)
)

class Interface(SimpleInterface):
	def __init__(self):
		super().__init__(_desc)

class Interconnect(SimpleInterconnect):
	pass
fhdl: simpler syntax 2011-12-16 15:30:14 -05:00			`from migen.fhdl.structure import *`
bus: simplify and cleanup Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups 2012-02-15 10:30:16 -05:00			`from migen.bus.simple import *`
CSR bus definitions 2011-12-04 18:16:44 -05:00
bus: simplify and cleanup Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups 2012-02-15 10:30:16 -05:00			`_desc = Description(`
			`(M_TO_S, "adr", 14),`
			`(M_TO_S, "we", 1),`
			`(M_TO_S, "dat_w", 8),`
			`(S_TO_M, "dat_r", 8)`
			`)`
Simple bus base class 2011-12-08 12:47:32 -05:00
bus: simplify and cleanup Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups 2012-02-15 10:30:16 -05:00			`class Interface(SimpleInterface):`
Remove explicit bus names and rely on the new automatic namer 2012-01-27 16:20:57 -05:00			`def __init__(self):`
Use super() instead of calling parent constructors directly 2012-06-08 12:06:12 -04:00			`super().__init__(_desc)`
CSR bus definitions 2011-12-04 18:16:44 -05:00
bus: simplify and cleanup Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups 2012-02-15 10:30:16 -05:00			`class Interconnect(SimpleInterconnect):`
			`pass`