26 lines
714 B
Python
26 lines
714 B
Python
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC
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class SimpleSoC(GenSoC):
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def __init__(self, platform):
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GenSoC.__init__(self, platform,
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clk_freq=32*1000000,
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cpu_reset_address=0,
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sram_size=4096)
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# We can't use reset_less as LM32 does require a reset signal
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self.clock_domains.cd_sys = ClockDomain()
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self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
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self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
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self.submodules.rom = wishbone.SRAM(32768)
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self.register_rom(self.rom.bus)
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def init_bios_memory(self, data):
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self.rom.mem.init = data
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def get_default_subtarget(platform):
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return SimpleSoC
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