litex/misoclib/mem/litesata/doc/source/home_page_layout.html

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<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>

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			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
			<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
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			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
			<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit
			user's needs! (Number of crossbar ports, included BIST and so on...)</p></div>
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			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
			<div class="signpost-body" style=""><p>Porting the core to another vendor or family only require adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
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