litex/examples/basic/complex.py

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2013-02-22 17:19:37 -05:00
from migen.genlib.complex import *
2013-01-05 08:18:36 -05:00
from migen.fhdl import verilog
w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16, variable=True)
C = SignalC(16)
D = SignalC(16)
sync = [
Bw.eq(B*w),
C.eq(A + Bw),
D.eq(A - Bw)
]
print(verilog.convert(Fragment(sync=sync)))