2015-03-01 12:27:46 -05:00
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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os, subprocess
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from migen.fhdl.std import *
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from migen.fhdl.structure import _Fragment
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from mibuild.generic_platform import *
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2015-03-27 09:14:49 -04:00
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from mibuild import tools
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from mibuild.sim import common
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def _build_tb(platform, vns, serial, template):
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2015-03-01 12:27:46 -05:00
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def io_name(ressource, subsignal=None):
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res = platform.lookup_request(ressource)
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if subsignal is not None:
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res = getattr(res, subsignal)
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2015-03-27 09:14:49 -04:00
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return vns.get_name(res)
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2015-03-01 12:27:46 -05:00
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ios = """
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#define SYS_CLK dut->{sys_clk}
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2015-03-06 06:20:17 -05:00
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""".format(sys_clk=io_name("sys_clk"))
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2015-03-01 12:27:46 -05:00
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2015-03-09 18:31:11 -04:00
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if serial == "pty":
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ios += "#define WITH_SERIAL_PTY"
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elif serial == "console":
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pass
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else:
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raise ValueError
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try:
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ios += """
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2015-03-01 12:27:46 -05:00
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#define SERIAL_SOURCE_STB dut->{serial_source_stb}
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#define SERIAL_SOURCE_ACK dut->{serial_source_ack}
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#define SERIAL_SOURCE_DATA dut->{serial_source_data}
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#define SERIAL_SINK_STB dut->{serial_sink_stb}
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#define SERIAL_SINK_ACK dut->{serial_sink_ack}
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#define SERIAL_SINK_DATA dut->{serial_sink_data}
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""".format(
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serial_source_stb=io_name("serial", "source_stb"),
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serial_source_ack=io_name("serial", "source_ack"),
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serial_source_data=io_name("serial", "source_data"),
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serial_sink_stb=io_name("serial", "sink_stb"),
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serial_sink_ack=io_name("serial", "sink_ack"),
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serial_sink_data=io_name("serial", "sink_data"),
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)
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except:
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pass
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try:
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ios += """
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#define ETH_SOURCE_STB dut->{eth_source_stb}
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#define ETH_SOURCE_ACK dut->{eth_source_ack}
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#define ETH_SOURCE_DATA dut->{eth_source_data}
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#define ETH_SINK_STB dut->{eth_sink_stb}
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#define ETH_SINK_ACK dut->{eth_sink_ack}
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#define ETH_SINK_DATA dut->{eth_sink_data}
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""".format(
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eth_source_stb=io_name("eth", "source_stb"),
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eth_source_ack=io_name("eth", "source_ack"),
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eth_source_data=io_name("eth", "source_data"),
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eth_sink_stb=io_name("eth", "sink_stb"),
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eth_sink_ack=io_name("eth", "sink_ack"),
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eth_sink_data=io_name("eth", "sink_data"),
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)
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except:
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pass
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2015-03-01 12:27:46 -05:00
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content = ""
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f = open(template, "r")
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done = False
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for l in f:
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content += l
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if "/* ios */" in l and not done:
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content += ios
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done = True
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f.close()
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tools.write_to_file("dut_tb.cpp", content)
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2015-03-27 09:14:49 -04:00
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def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbose):
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include = ""
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for path in include_paths:
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include += "-I"+path+" "
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build_script_contents = """# Autogenerated by mibuild
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rm -rf obj_dir/
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2015-03-03 11:35:52 -05:00
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verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp -LDFLAGS "-lpthread" -trace {include}
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make -j -C obj_dir/ -f Vdut.mk Vdut
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2015-03-02 17:23:23 -05:00
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""".format(
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disable_warnings="-Wno-fatal",
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include=include)
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
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2015-03-27 09:14:49 -04:00
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_build_tb(platform, vns, serial, os.path.join("..", sim_path,"dut_tb.cpp"))
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2015-03-02 17:23:23 -05:00
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if verbose:
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r = subprocess.call(["bash", build_script_file])
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else:
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r = subprocess.call(["bash", build_script_file], stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT)
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if r != 0:
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raise OSError("Subprocess failed")
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def _run_sim(build_name):
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run_script_contents = """obj_dir/Vdut
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"""
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run_script_file = "run_" + build_name + ".sh"
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tools.write_to_file(run_script_file, run_script_contents, force_unix=True)
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r = subprocess.call(["bash", run_script_file])
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if r != 0:
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raise OSError("Subprocess failed")
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class SimVerilatorToolchain:
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# XXX fir sim_path
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def build(self, platform, fragment, build_dir="build", build_name="top",
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sim_path="../migen/mibuild/sim/", serial="console",
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run=True, verbose=False):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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2015-03-27 09:14:49 -04:00
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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v_src, vns = platform.get_verilog(fragment)
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named_sc, named_pc = platform.resolve_signals(vns)
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v_file = "dut.v"
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tools.write_to_file(v_file, v_src)
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include_paths = []
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for source in platform.sources:
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path = os.path.dirname(source[0]).replace("\\", "\/")
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if path not in include_paths:
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include_paths.append(path)
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include_paths += platform.verilog_include_paths
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_build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbose)
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2015-03-01 12:27:46 -05:00
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if run:
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_run_sim(build_name)
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os.chdir("..")
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2015-03-27 09:14:49 -04:00
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return vns
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