122 lines
3.7 KiB
Python
122 lines
3.7 KiB
Python
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.actorlib.fifo import SyncFIFO as FIFO
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from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.frontend.dma.common import *
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from misoclib.com.litepcie.frontend.dma.writer import DMAWriter
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from misoclib.com.litepcie.frontend.dma.reader import DMAReader
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class DMALoopback(Module, AutoCSR):
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def __init__(self, dw):
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self._enable = CSRStorage()
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self.sink = Sink(dma_layout(dw))
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self.source = Source(dma_layout(dw))
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self.next_source = Source(dma_layout(dw))
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self.next_sink = Sink(dma_layout(dw))
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# # #
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enable = self._enable.storage
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self.comb += \
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If(enable,
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Record.connect(self.sink, self.source)
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).Else(
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Record.connect(self.sink, self.next_source),
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Record.connect(self.next_sink, self.source)
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)
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class DMASynchronizer(Module, AutoCSR):
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def __init__(self, dw):
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self._bypass = CSRStorage()
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self._enable = CSRStorage()
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self.ready = Signal(reset=1)
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self.pps = Signal()
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self.sink = Sink(dma_layout(dw))
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self.source = Source(dma_layout(dw))
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self.next_source = Source(dma_layout(dw))
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self.next_sink = Sink(dma_layout(dw))
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# # #
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bypass = self._bypass.storage
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enable = self._enable.storage
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synced = Signal()
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self.sync += \
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If(~enable,
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synced.eq(0)
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).Else(
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If(self.ready & self.sink.stb & (self.pps | bypass),
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synced.eq(1)
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)
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)
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self.comb += \
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If(synced,
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Record.connect(self.sink, self.next_source),
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Record.connect(self.next_sink, self.source),
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).Else(
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# Block sink
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self.next_source.stb.eq(0),
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self.sink.ack.eq(0),
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# Ack next_sink
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self.source.stb.eq(0),
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self.next_sink.ack.eq(1),
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)
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class DMABuffering(Module, AutoCSR):
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def __init__(self, dw, depth):
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tx_fifo = FIFO(dma_layout(dw), depth//(dw//8), buffered=True)
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rx_fifo = FIFO(dma_layout(dw), depth//(dw//8), buffered=True)
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self.submodules += tx_fifo, rx_fifo
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self.sink = tx_fifo.sink
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self.source = rx_fifo.source
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self.next_source = tx_fifo.source
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self.next_sink = rx_fifo.sink
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class DMA(Module, AutoCSR):
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def __init__(self, phy, endpoint,
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with_buffering=False, buffering_depth=256*8,
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with_loopback=False,
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with_synchronizer=False):
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# Writer, Reader
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self.submodules.writer = DMAWriter(endpoint, endpoint.crossbar.get_master_port(write_only=True))
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self.submodules.reader = DMAReader(endpoint, endpoint.crossbar.get_master_port(read_only=True))
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self.sink, self.source = self.writer.sink, self.reader.source
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# Loopback
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if with_loopback:
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self.submodules.loopback = DMALoopback(phy.dw)
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self.insert_optional_module(self.loopback)
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# Synchronizer
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if with_synchronizer:
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self.submodules.synchronizer = DMASynchronizer(phy.dw)
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self.insert_optional_module(self.synchronizer)
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# Buffering
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if with_buffering:
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self.submodules.buffering = DMABuffering(phy.dw, buffering_depth)
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self.insert_optional_module(self.buffering)
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def insert_optional_module(self, m):
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self.comb += [
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Record.connect(self.source, m.sink),
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Record.connect(m.source, self.sink)
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]
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self.sink, self.source = m.next_sink, m.next_source
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