32 lines
923 B
Python
32 lines
923 B
Python
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC, IntegratedBIOS
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class BaseSoC(GenSoC, IntegratedBIOS):
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default_platform = "kc705"
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def __init__(self, platform, **kwargs):
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GenSoC.__init__(self, platform,
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clk_freq=156*1000000, cpu_reset_address=0,
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**kwargs)
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IntegratedBIOS.__init__(self)
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clk200 = platform.request("clk156")
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self.specials += Instance("IBUFGDS",
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i_I=clk200.p,
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i_IB=clk200.n,
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o_O=ClockSignal()
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)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True)
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self.comb += self.cd_pwr_on.clk.eq(self.cd_sys.clk)
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self.cd_sys.rst.reset = 1
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self.sync.pwr_on += self.cd_sys.rst.eq(0)
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self.submodules.usermem = wishbone.SRAM(64*1024)
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self.add_wb_slave(lambda a: a[27:29] == 2, self.usermem.bus)
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self.add_cpu_memory_region("sdram", 0x40000000, 64*1024)
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default_subtarget = BaseSoC
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