litex/misoclib/mem/sdram/__init__.py

from collections import namedtuple

PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
	return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)

GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
def GeomSettings(bankbits, rowbits, colbits):
	return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))

TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
Refactor directory hierarchy of sdram phys and controllers 2014-11-26 04:37:50 -05:00			`from collections import namedtuple`

sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-24 12:25:59 -04:00			`PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")`
			`def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):`
			`return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)`
Refactor directory hierarchy of sdram phys and controllers 2014-11-26 04:37:50 -05:00
sdram: remove nbits from modules and databits from GeomSettings 2015-03-26 18:27:37 -04:00			`GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")`
			`def GeomSettings(bankbits, rowbits, colbits):`
			`return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))`
Refactor directory hierarchy of sdram phys and controllers 2014-11-26 04:37:50 -05:00
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings 2015-03-21 07:55:39 -04:00			`TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")`