2012-02-16 12:02:37 -05:00
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from fractions import Fraction
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2013-05-22 11:10:13 -04:00
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from migen.fhdl.std import *
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2012-02-16 12:02:37 -05:00
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2015-04-13 10:47:22 -04:00
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2013-09-17 12:15:22 -04:00
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class MXCRG(Module):
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2015-04-13 10:19:55 -04:00
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def __init__(self, pads, outfreq1x):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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self.clock_domains.cd_base50 = ClockDomain(reset_less=True)
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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###
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infreq = 50*1000000
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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self.specials += Instance("mxcrg",
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2015-04-13 11:56:51 -04:00
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Instance.Parameter("in_period", in_period),
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Instance.Parameter("f_mult", ratio.numerator),
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Instance.Parameter("f_div", ratio.denominator),
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Instance.Input("clk50_pad", pads.clk50),
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Instance.Input("trigger_reset", pads.trigger_reset),
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Instance.Output("sys_clk", self.cd_sys.clk),
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Instance.Output("sys_rst", self.cd_sys.rst),
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Instance.Output("clk2x_270", self.cd_sdram_half.clk),
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Instance.Output("clk4x_wr", self.cd_sdram_full_wr.clk),
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Instance.Output("clk4x_rd", self.cd_sdram_full_rd.clk),
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Instance.Output("base50_clk", self.cd_base50.clk),
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Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
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Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
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Instance.Output("norflash_rst_n", pads.norflash_rst_n),
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Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
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Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n))
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