92 lines
2.1 KiB
Python
92 lines
2.1 KiB
Python
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from liteeth.common import *
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from liteeth.core.etherbone import common
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class LiteEthEtherboneWishboneMaster(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_user_description(32))
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self.source = source = Source(eth_etherbone_description(32))
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self.bus = bus = wishbone.Interface()
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###
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += self.base_addr.d.eq(self.sink.data)
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self.submodules.counter = counter = Counter(32)
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self.submodules.fifo = fifo = SyncFIFO([("data", 32)], 256)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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If(sink.wcount > 0,
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self.base_addr.ce.eq(1),
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NextState("WRITE_DATA")
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).Elif(sink.rcount > 0,
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self.base_addr.ce.eq(1),
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NextState("READ_DATA")
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)
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)
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)
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fsm.act("WRITE_DATA",
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bus.adr.eq(base_addr + self.counter.value),
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bus.dat_w.eq(sink.data),
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bus.sel.eq(0xf), # XXX?
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bus.stb.eq(sink.stb),
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bus.we.eq(1),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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sink.ack.eq(1),
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counter.ce.eq(1),
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If(counter.value == sink.wcount-1,
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If(sink.rcount > 0,
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counter.reset.eq(1)
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NextState("READ_DATA")
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).Else(
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NextState("TERMINATE")
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)
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)
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)
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)
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fsm.act("CHECK_READ",
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If(sink.rcount > 0,
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If(sink.stb,
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sink.ack.eq(1),
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base_addr.ce.eq(1),
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NextState("READ_DATA")
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)
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).Else(
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NextState("IDLE")
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)
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)
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fsm.act("READ_DATA",
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bus.adr.eq(self.sink.data),
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bus.sel.eq(0xf),
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bus.stb.eq(1),
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bus.we.eq(0),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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sink.ack.eq(1),
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counter.ce.eq(1),
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fifo.sink.stb.eq(1),
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fifo.sink.sop.eq(counter == 0),
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fifo.sink.data.eq(bus.dat_r),
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If(counter.value == sink.rcount-1,
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fifo.sink.eop.eq(1),
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NextState("PRESENT_DATA")
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)
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)
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)
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fsm.act("PRESENT_DATA",
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source.stb.eq(fifo.stb),
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source.sop.eq(fifo.sop),
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source.eop.eq(fifo.eop),
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fifo.ack.eq(source.ack),
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source.length.eq(sink.rcount+1),
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source.wcount.eq(sink.rcount),
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source.rcount.eq(0),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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