2015-02-09 05:19:26 -05:00
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from liteeth.common import *
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2015-02-11 19:19:36 -05:00
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from liteeth.generic import *
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2015-02-10 09:22:06 -05:00
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2015-02-11 19:30:17 -05:00
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from liteeth.generic.crossbar import LiteEthCrossbar
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2015-02-09 05:19:26 -05:00
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class LiteEthUDPMasterPort:
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def __init__(self, dw):
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2015-02-10 04:30:39 -05:00
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self.dw = dw
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2015-02-09 05:19:26 -05:00
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self.source = Source(eth_udp_user_description(dw))
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self.sink = Sink(eth_udp_user_description(dw))
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class LiteEthUDPSlavePort:
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def __init__(self, dw):
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2015-02-10 04:30:39 -05:00
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self.dw =dw
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2015-02-09 05:19:26 -05:00
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self.sink = Sink(eth_udp_user_description(dw))
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self.source = Source(eth_udp_user_description(dw))
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class LiteEthUDPUserPort(LiteEthUDPSlavePort):
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def __init__(self, dw):
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LiteEthUDPSlavePort.__init__(self, dw)
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2015-02-10 09:22:06 -05:00
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class LiteEthUDPCrossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
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def get_port(self, udp_port, dw=8):
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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user_port = LiteEthUDPUserPort(dw)
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internal_port = LiteEthUDPUserPort(8)
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if dw != 8:
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converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
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self.submodules += converter
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self.comb += [
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Record.connect(user_port.sink, converter.sink),
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Record.connect(converter.source, internal_port.sink)
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]
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converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
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self.submodules += converter
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self.comb += [
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Record.connect(internal_port.source, converter.sink),
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Record.connect(converter.source, user_port.source)
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]
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self.users[udp_port] = internal_port
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else:
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self.users[udp_port] = user_port
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return user_port
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