84 lines
1.8 KiB
Python
84 lines
1.8 KiB
Python
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from migen.fhdl.std import *
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from lib.sata.std import *
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from lib.sata.link import crc
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from lib.sata.link import scrambler
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class SATALinkLayerTX(Module):
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def __init__(self, dw):
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self.sink = Sink(link_layout(dw))
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self.source = Source(phy_layout(dw))
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###
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# insert CRC
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crc_inserter = crc.SATACRCInserter(link_layout(dw))
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self.submodules += crc_inserter
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# scramble
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scrambler = scrambler.SATAScrambler(link_layout(dw))
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self.submodules += scrambler
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class SATALinkLayerRX(Module):
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def __init__(self, dw):
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self.sink = Sink(link_layout(dw))
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self.source = Source(phy_layout(dw))
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###
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# descramble
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descrambler = descrambler.SATAScrambler(link_layout(dw))
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self.submodules += descrambler
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# check CRC
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crc_checker = crc.SATACRCChecker(link_layout(dw))
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self.submodules += crc_checker
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class SATALinkLayer(Module):
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def __init__(self, phy, dw=32):
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self.submodules.tx = SATALinkLayerTX(dw)
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self.submodules.rx = SATALinkLayerRX(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(SYNC_VAL),
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NextState("RDY")
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)
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fsm.act("RDY",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(X_RDY_VAL)
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If(phy.source.stb & (phy.source.d == X_RDY_VAL),
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NextState("SOF")
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)
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fsm.act("SOF",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(SOF_VAL),
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NextState("COPY")
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)
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fsm.act("COPY",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(),
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NextState("EOF")
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)
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fsm.act("EOF",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(EOF_VAL),
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NextState("")
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)
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fsm.act("EOF",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(EOF_VAL),
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NextState("")
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)
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fsm.act("WTRM",
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phy.sink.stb.eq(1),
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phy.sink.d.eq(WTRM_VAL),
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If(phy.source.stb & (phy.source.d == R_OK_VAL),
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NextState("IDLE")
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).Elif(phy.source.stb & (phy.source.d == R_ERR_VAL),
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NextState("IDLE")
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)
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)
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