litex/test/test_i2s.py

# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD

import unittest

from migen import *

from litex.soc.cores.i2s import S7I2S


class TestI2S(unittest.TestCase):
    def test_s7i2sslave_syntax(self):
        i2s_pads = Record([("rx", 1), ("tx", 1), ("sync", 1), ("clk", 1)])
        i2s = S7I2S(pads=i2s_pads, fifo_depth=256)
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 11:00:04 -05:00			`# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>`
			`# License: BSD`

			`import unittest`

			`from migen import *`

Extend I2S capabilities This commit: * adds the support for I2S standard mode, * extends I2S left justified mode, * allows to configure sample size for tx/rx in 1-32 bits range, * implements I2S master mode, * allows to concatenate channels or used the padded mode. This required to rework the FSM. 2020-03-12 09:54:41 -04:00			`from litex.soc.cores.i2s import S7I2S`
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 11:00:04 -05:00

			`class TestI2S(unittest.TestCase):`
			`def test_s7i2sslave_syntax(self):`
			`i2s_pads = Record([("rx", 1), ("tx", 1), ("sync", 1), ("clk", 1)])`
Extend I2S capabilities This commit: * adds the support for I2S standard mode, * extends I2S left justified mode, * allows to configure sample size for tx/rx in 1-32 bits range, * implements I2S master mode, * allows to concatenate channels or used the padded mode. This required to rework the FSM. 2020-03-12 09:54:41 -04:00			`i2s = S7I2S(pads=i2s_pads, fifo_depth=256)`
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 11:00:04 -05:00