45 lines
1.0 KiB
Python
45 lines
1.0 KiB
Python
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from migen.fhdl.std import *
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from migen.bank.description import *
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class Bandwidth(Module, AutoCSR):
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def __init__(self, cmd, period_bits=24):
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self._r_update = CSR()
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self._r_nreads = CSRStatus(period_bits)
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self._r_nwrites = CSRStatus(period_bits)
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###
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cmd_stb = Signal()
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cmd_ack = Signal()
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cmd_is_read = Signal()
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cmd_is_write = Signal()
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self.sync += [
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cmd_stb.eq(cmd.stb),
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cmd_ack.eq(cmd.ack),
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cmd_is_read.eq(cmd.is_read),
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cmd_is_write.eq(cmd.is_write)
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]
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counter = Signal(period_bits)
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period = Signal()
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nreads = Signal(period_bits)
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nwrites = Signal(period_bits)
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nreads_r = Signal(period_bits)
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nwrites_r = Signal(period_bits)
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self.sync += [
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Cat(counter, period).eq(counter + 1),
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If(period,
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nreads_r.eq(nreads),
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nwrites_r.eq(nwrites),
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nreads.eq(0),
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nwrites.eq(0)
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).Elif(cmd_stb & cmd_ack,
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If(cmd_is_read, nreads.eq(nreads + 1)),
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If(cmd_is_write, nwrites.eq(nwrites + 1)),
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),
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If(self._r_update.re,
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self._r_nreads.status.eq(nreads_r),
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self._r_nwrites.status.eq(nwrites_r)
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)
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]
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