76 lines
2.1 KiB
Python
76 lines
2.1 KiB
Python
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from migen.fhdl.structure import *
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from migen.corelogic.record import *
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from migen.corelogic.fsm import *
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from migen.bus import wishbone
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from migen.flow.actor import *
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class Reader(Actor):
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def __init__(self, layout):
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self.address = Record([("a", BV(30))])
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self.data = Record(layout)
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self.bus = wishbone.Master()
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Actor.__init__(self,
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SchedulingModel(SchedulingModel.DYNAMIC),
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self.address, self.data)
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def get_fragment(self):
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components, length = self.data.flatten(align=True, return_offset=True)
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nwords = (length + 31)//32
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# Address generator
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ag_stb = Signal()
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ag_sync = [If(ag_stb, self.bus.adr_o.eq(self.address.a))]
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if nwords > 1:
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ag_inc = Signal()
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sync.append(If(ag_inc, self.bus.adr_o.eq(self.bus.adr_o + 1)))
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address_generator = Fragment(sync=ag_sync)
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# Output buffer
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ob_reg = Signal(BV(length))
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ob_stbs = Signal(BV(nwords))
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ob_sync = [If(ob_stbs[w], ob_reg[32*w:32*(w+1)].eq(self.bus.dat_i))
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for w in range(nwords)]
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ob_comb = []
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offset = 0
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for s in components:
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w = s.bv.width
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if isinstance(s, Signal):
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comb.append(s.eq(ob_reg[length-offset-w:length-offset]))
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offset += w
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output_buffer = Fragment(ob_comb, ob_sync)
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# Controller
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fetch_states = ["FETCH{0}".format(w) for w in range(nwords)]
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states = ["IDLE"] + fetch_states + ["STROBE"]
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fsm = FSM(*states)
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self.busy.reset = Constant(1)
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fsm.act(fsm.IDLE,
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self.busy.eq(0),
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ag_stb.eq(1),
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self.endpoints["address"].ack.eq(1),
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If(self.endpoints["address"].stb, fsm.next_state(fsm.FETCH0))
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)
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for w in range(nwords):
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state = getattr(fsm, fetch_states[w])
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if w == nwords - 1:
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next_state = fsm.STROBE
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else:
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state = getattr(fsm, fetch_states[w+1])
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fsm.act(state,
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self.bus.cyc_o.eq(1),
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self.bus.stb_o.eq(1),
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If(self.bus.ack_i,
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ob_stbs[nwords-w-1].eq(1),
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fsm.next_state(next_state)
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)
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)
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if nwords > 1:
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fsm.act(state, If(self.bus.ack_i, ag_inc.eq(1)))
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fsm.act(fsm.STROBE,
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self.endpoints["data"].stb.eq(1),
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If(self.endpoints["data"].ack, fsm.next_state(fsm.IDLE))
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)
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controller = fsm.get_fragment()
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return address_generator + output_buffer + controller
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