litex/examples/basic/reslice.py

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from migen.fhdl.std import *
from migen.fhdl import verilog
2015-04-13 14:45:35 -04:00
class Example(Module):
def __init__(self):
a = Signal(3)
b = Signal(4)
c = Signal(5)
d = Signal(7)
s1 = c[:3][:2]
s2 = Cat(a, b)[:6]
s3 = Cat(s1, s2)[-5:]
self.comb += s3.eq(0)
self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
print(verilog.convert(Example()))