litex/MANIFEST.in

graft litex/build/sim
graft litex/soc/software
graft litex/soc/cores/cpu/lm32/verilog
graft litex/soc/cores/cpu/minerva/verilog
graft litex/soc/cores/cpu/mor1kx/verilog
graft litex/soc/cores/cpu/picorv32/verilog
graft litex/soc/cores/cpu/rocket/verilog
graft litex/soc/cores/cpu/vexriscv/verilog
litex: get verilator simulation working and add sim target as example 2015-11-07 17:51:37 -05:00			`graft litex/build/sim`
litex: reorganize things, first work working version 2015-11-07 06:26:46 -05:00			`graft litex/soc/software`
			`graft litex/soc/cores/cpu/lm32/verilog`
Add verilog submodule from CPU cores to manifest 2019-07-03 18:58:26 -04:00			`graft litex/soc/cores/cpu/minerva/verilog`
litex: reorganize things, first work working version 2015-11-07 06:26:46 -05:00			`graft litex/soc/cores/cpu/mor1kx/verilog`
Add verilog submodule from CPU cores to manifest 2019-07-03 18:58:26 -04:00			`graft litex/soc/cores/cpu/picorv32/verilog`
			`graft litex/soc/cores/cpu/rocket/verilog`
			`graft litex/soc/cores/cpu/vexriscv/verilog`