14 lines
341 B
Python
14 lines
341 B
Python
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from migen.fhdl.std import *
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from migen.genlib.crc import CRC32
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self, width):
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crc32 = CRC32(width)
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self.submodules += crc32
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self.ios = {crc32.reset, crc32.ce,
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crc32.d, crc32.value, crc32.error}
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example = Example(8)
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print(verilog.convert(example, example.ios))
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