2012-10-31 10:59:12 -04:00
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import inspect
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import ast
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2012-11-09 11:37:42 -05:00
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from operator import itemgetter
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2012-10-31 10:59:12 -04:00
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from migen.fhdl.structure import *
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2012-11-09 11:37:42 -05:00
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from migen.fhdl import visit as fhdl
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from migen.corelogic.fsm import FSM
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2012-10-31 10:59:12 -04:00
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from migen.pytholite import transel
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class FinalizeError(Exception):
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pass
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class _AbstractLoad:
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def __init__(self, target, source):
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self.target = target
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self.source = source
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2012-11-09 11:37:42 -05:00
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def lower(self):
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if not self.target.finalized:
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raise FinalizeError
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return self.target.sel.eq(self.target.source_encoding[self.source])
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class _LowerAbstractLoad(fhdl.NodeTransformer):
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def visit_unknown(self, node):
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if isinstance(node, _AbstractLoad):
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return node.lower()
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else:
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return node
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2012-10-31 10:59:12 -04:00
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class _Register:
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def __init__(self, name, nbits):
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self.storage = Signal(BV(nbits), name=name)
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self.source_encoding = {}
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self.finalized = False
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def load(self, source):
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if source not in self.source_encoding:
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self.source_encoding[source] = len(self.source_encoding) + 1
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return _AbstractLoad(self, source)
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def finalize(self):
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if self.finalized:
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raise FinalizeError
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2012-11-09 11:37:42 -05:00
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self.sel = Signal(BV(bits_for(len(self.source_encoding) + 1)), name="pl_regsel")
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2012-10-31 10:59:12 -04:00
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self.finalized = True
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def get_fragment(self):
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if not self.finalized:
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raise FinalizeError
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# do nothing when sel == 0
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2012-11-09 11:37:42 -05:00
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items = sorted(self.source_encoding.items(), key=itemgetter(1))
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2012-11-08 15:49:20 -05:00
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cases = [(Constant(v, self.sel.bv),
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2012-11-09 11:37:42 -05:00
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self.storage.eq(k)) for k, v in items]
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2012-10-31 10:59:12 -04:00
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sync = [Case(self.sel, *cases)]
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return Fragment(sync=sync)
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2012-11-09 13:37:52 -05:00
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class _AbstractNextState:
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def __init__(self, target_state):
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self.target_state = target_state
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2012-11-06 07:52:19 -05:00
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class _Compiler:
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2012-10-31 10:59:12 -04:00
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def __init__(self, symdict, registers):
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self.symdict = symdict
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self.registers = registers
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2012-11-06 07:52:19 -05:00
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self.targetname = ""
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2012-10-31 10:59:12 -04:00
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2012-11-06 07:52:19 -05:00
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def visit_top(self, node):
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if isinstance(node, ast.Module) \
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and len(node.body) == 1 \
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and isinstance(node.body[0], ast.FunctionDef):
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2012-11-09 14:12:15 -05:00
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states, exit_states = self.visit_block(node.body[0].body)
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return states
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2012-11-06 07:52:19 -05:00
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else:
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raise NotImplementedError
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# blocks and statements
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def visit_block(self, statements):
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states = []
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exit_states = []
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for statement in statements:
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n_states, n_exit_states = self.visit_statement(statement)
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if n_states:
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states += n_states
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for exit_state in exit_states:
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exit_state.insert(0, _AbstractNextState(n_states[0]))
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exit_states = n_exit_states
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return states, exit_states
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# entry state is first state returned
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def visit_statement(self, statement):
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states = []
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exit_states = []
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if isinstance(statement, ast.Assign):
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op = self.visit_assign(statement)
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if op:
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states.append(op)
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exit_states.append(op)
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elif isinstance(statement, ast.If):
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test = self.visit_expr(statement.test)
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states_t, exit_states_t = self.visit_block(statement.body)
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states_f, exit_states_f = self.visit_block(statement.orelse)
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test_state_stmt = If(test, _AbstractNextState(states_t[0]))
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test_state = [test_state_stmt]
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if states_f:
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test_state_stmt.Else(_AbstractNextState(states_f[0]))
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else:
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exit_states.append(test_state)
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states.append(test_state)
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states += states_t + states_f
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exit_states += exit_states_t + exit_states_f
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else:
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raise NotImplementedError
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return states, exit_states
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2012-11-06 07:52:19 -05:00
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def visit_assign(self, node):
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if isinstance(node.targets[0], ast.Name):
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self.targetname = node.targets[0].id
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value = self.visit_expr(node.value, True)
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self.targetname = ""
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if isinstance(value, _Register):
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2012-10-31 10:59:12 -04:00
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self.registers.append(value)
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for target in node.targets:
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if isinstance(target, ast.Name):
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self.symdict[target.id] = value
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else:
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raise NotImplementedError
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2012-11-06 07:52:19 -05:00
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return []
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elif isinstance(value, Value):
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r = []
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for target in node.targets:
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if isinstance(target, ast.Attribute) and target.attr == "store":
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treg = target.value
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if isinstance(treg, ast.Name):
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r.append(self.symdict[treg.id].load(value))
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else:
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raise NotImplementedError
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else:
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raise NotImplementedError
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return r
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else:
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raise NotImplementedError
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2012-10-31 10:59:12 -04:00
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2012-11-06 07:52:19 -05:00
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# expressions
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def visit_expr(self, node, allow_call=False):
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if isinstance(node, ast.Call):
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if allow_call:
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return self.visit_expr_call(node)
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else:
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raise NotImplementedError
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elif isinstance(node, ast.BinOp):
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return self.visit_expr_binop(node)
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2012-11-09 12:41:32 -05:00
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elif isinstance(node, ast.Compare):
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return self.visit_expr_compare(node)
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2012-11-06 07:52:19 -05:00
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elif isinstance(node, ast.Name):
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return self.visit_expr_name(node)
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elif isinstance(node, ast.Num):
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return self.visit_expr_num(node)
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else:
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raise NotImplementedError
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def visit_expr_call(self, node):
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2012-10-31 10:59:12 -04:00
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if isinstance(node.func, ast.Name):
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callee = self.symdict[node.func.id]
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else:
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raise NotImplementedError
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if callee == transel.Register:
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if len(node.args) != 1:
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raise TypeError("Register() takes exactly 1 argument")
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nbits = ast.literal_eval(node.args[0])
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return _Register(self.targetname, nbits)
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else:
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raise NotImplementedError
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2012-11-06 07:52:19 -05:00
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def visit_expr_binop(self, node):
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left = self.visit_expr(node.left)
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right = self.visit_expr(node.right)
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if isinstance(node.op, ast.Add):
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return left + right
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elif isinstance(node.op, ast.Sub):
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return left - right
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elif isinstance(node.op, ast.Mult):
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return left * right
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elif isinstance(node.op, ast.LShift):
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return left << right
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elif isinstance(node.op, ast.RShift):
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return left >> right
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elif isinstance(node.op, ast.BitOr):
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return left | right
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elif isinstance(node.op, ast.BitXor):
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return left ^ right
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elif isinstance(node.op, ast.BitAnd):
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return left & right
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else:
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raise NotImplementedError
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2012-11-09 12:41:32 -05:00
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def visit_expr_compare(self, node):
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test = self.visit_expr(node.left)
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2012-11-09 12:41:32 -05:00
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r = None
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for op, rcomparator in zip(node.ops, node.comparators):
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comparator = self.visit_expr(rcomparator)
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if isinstance(op, ast.Eq):
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comparison = test == comparator
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elif isinstance(op, ast.NotEq):
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comparison = test != comparator
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elif isinstance(op, ast.Lt):
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comparison = test < comparator
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elif isinstance(op, ast.LtE):
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comparison = test <= comparator
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elif isinstance(op, ast.Gt):
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comparison = test > comparator
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elif isinstance(op, ast.GtE):
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comparison = test >= comparator
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else:
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raise NotImplementedError
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if r is None:
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r = comparison
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else:
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r = r & comparison
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test = comparator
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return r
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2012-11-06 07:52:19 -05:00
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def visit_expr_name(self, node):
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r = self.symdict[node.id]
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if isinstance(r, _Register):
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r = r.storage
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return r
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def visit_expr_num(self, node):
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return Constant(node.n)
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2012-11-09 13:37:52 -05:00
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# like list.index, but using "is" instead of comparison
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def _index_is(l, x):
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for i, e in enumerate(l):
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if e is x:
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return i
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class _LowerAbstractNextState(fhdl.NodeTransformer):
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def __init__(self, fsm, states, stnames):
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self.fsm = fsm
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self.states = states
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self.stnames = stnames
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def visit_unknown(self, node):
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if isinstance(node, _AbstractNextState):
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index = _index_is(self.states, node.target_state)
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estate = getattr(self.fsm, self.stnames[index])
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return self.fsm.next_state(estate)
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else:
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return node
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2012-11-09 11:37:42 -05:00
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def _create_fsm(states):
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stnames = ["S" + str(i) for i in range(len(states))]
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fsm = FSM(*stnames)
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lans = _LowerAbstractNextState(fsm, states, stnames)
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for i, state in enumerate(states):
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actions = lans.visit(state)
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fsm.act(getattr(fsm, stnames[i]), *actions)
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return fsm
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2012-10-31 10:59:12 -04:00
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def make_pytholite(func):
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tree = ast.parse(inspect.getsource(func))
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symdict = func.__globals__.copy()
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registers = []
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2012-11-09 12:41:32 -05:00
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print("ast:")
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print(ast.dump(tree))
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2012-11-08 15:49:20 -05:00
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states = _Compiler(symdict, registers).visit_top(tree)
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2012-11-06 07:52:19 -05:00
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print("compilation result:")
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print(states)
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2012-10-31 10:59:12 -04:00
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2012-11-08 15:49:20 -05:00
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regf = Fragment()
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for register in registers:
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register.finalize()
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regf += register.get_fragment()
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2012-11-09 11:37:42 -05:00
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fsm = _create_fsm(states)
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fsmf = _LowerAbstractLoad().visit(fsm.get_fragment())
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return regf + fsmf
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