2013-05-07 04:30:56 -04:00
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("i2c", 0,
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Subsignal("scl", Pins("K21")),
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Subsignal("sda", Pins("L21")),
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IOStandard("LVCMOS25")),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")),
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("mmc", 0,
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Subsignal("wp", Pins("Y21")),
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Subsignal("det", Pins("AA21")),
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Subsignal("cmd", Pins("AB22")),
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Subsignal("clk", Pins("AB23")),
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2013-06-25 16:57:31 -04:00
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Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
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2013-05-07 04:30:56 -04:00
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IOStandard("LVCMOS25")),
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("lcd", 0,
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2013-06-25 16:57:31 -04:00
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Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
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2013-05-07 04:30:56 -04:00
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Subsignal("e", Pins("AB10")),
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Subsignal("rs", Pins("Y11")),
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Subsignal("rw", Pins("AB13")),
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IOStandard("LVCMOS15")),
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("rotary", 0,
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Subsignal("a", Pins("Y26")),
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Subsignal("b", Pins("Y25")),
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Subsignal("push", Pins("AA26")),
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IOStandard("LVCMOS25")),
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("hdmi", 0,
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2013-06-25 16:57:31 -04:00
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Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
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2013-05-07 04:30:56 -04:00
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Subsignal("de", Pins("H17")),
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Subsignal("clk", Pins("K18")),
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Subsignal("vsync", Pins("H20")),
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Subsignal("hsync", Pins("J18")),
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Subsignal("int", Pins("AH24")),
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Subsignal("spdif", Pins("J17")),
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Subsignal("spdif_out", Pins("G20")),
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IOStandard("LVCMOS25")),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "user_clk", "cpu_reset", 6.4)):
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XilinxISEPlatform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
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