2013-07-04 03:06:55 -04:00
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
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_io = [
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("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),
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("clk_if", 0, Pins("K20"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("A18")),
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# PROG_B and DONE: AA1 U16
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("fx2", 0,
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Subsignal("sloe", Pins("U15"), Drive(12)), # M1
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Subsignal("slrd", Pins("N22"), Drive(12)),
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Subsignal("slwr", Pins("M22"), Drive(12)),
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Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO
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Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0
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Subsignal("cont", Pins("G20")),
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Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 "
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"V21 V22 U20 U22 R20 R22 P18 P19")),
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Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI
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Subsignal("rdy25", Pins("M21 K21 K22 J21")),
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Subsignal("ctl35", Pins("D19 E20 N20")),
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Subsignal("int45", Pins("C18 V17")),
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Subsignal("pc", Pins("G20 T10 V5 AB9 G19 H20 H19 H18")),
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# - DOUT/BUSY INIT_B RDWR_B DO CS CLK DI
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IOStandard("LVCMOS33")),
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("mm", 0,
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Subsignal("a", Pins("M20 M19 M18 N19 T19 T21 T22 R19 ",
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"P20 P21 P22 J22 H21 H22 G22 F21")),
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Subsignal("d", Pins("D20 C20 C19 B21 B20 J19 K19 L19"), Drive(2)),
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Subsignal("wr_n", Pins("C22")),
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Subsignal("rd_n", Pins("D21")),
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Subsignal("psen_n", Pins("D22")),
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IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("B22"), Misc("SLEW=QUIETIO")),
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Subsignal("rx", Pins("A21"), Misc("PULLDOWN")),
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IOStandard("LVCMOS33")),
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("ddram_clock", 0,
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Subsignal("p", Pins("F2"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("n", Pins("F1"), Misc("OUT_TERM=UNTUNED_50")),
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IOStandard("SSTL18_II")),
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("ddram", 0,
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Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_
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Misc("IN_TERM=NONE")),
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Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_
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Misc("IN_TERM=NONE")),
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Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 "
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"U1 U3 P1 R3 P2 R1 V2 V1"), Misc("IN_TERM=NONE")),
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Subsignal("ras_n", Pins("N4"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("cas_n", Pins("P3"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("a", Pins("M5 K6 B1 J4 L4 K3 M4 K5 G3 G1 K4 C3 C1"),
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Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("cs_n", Pins("H6")), # NC!
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Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")),
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Subsignal("we_n", Pins("D2")),
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Subsignal("rzq", Pins("AA2")),
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Subsignal("zio", Pins("Y2")),
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IOStandard("SSTL18_II")),
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("i2c", 0,
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Subsignal("scl", Pins("F22")),
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Subsignal("sda", Pins("E22")),
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IOStandard("LVCMOS33")),
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("sd", 0,
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Subsignal("sck", Pins("H11")),
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Subsignal("d3", Pins("H14")),
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Subsignal("d", Pins("P10")),
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Subsignal("d1", Pins("T18")),
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Subsignal("d2", Pins("R17")),
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Subsignal("cmd", Pins("H13")),
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IOStandard("LVCMOS33")),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
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lambda p: CRG_SE(p, "clk_if", "rst"))
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self.add_platform_command("""
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CONFIG VCCAUX = "2.5";
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""")
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def do_finalize(self, fragment):
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try:
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2014-05-19 06:03:26 -04:00
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self.add_period_constraint(self.lookup_request("clk_if"), 20)
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2013-07-04 03:06:55 -04:00
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except ConstraintError:
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pass
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try:
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clk_if = self.lookup_request("clk_if")
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clk_fx = self.lookup_request("clk_fx")
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self.add_platform_command("""
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NET "{clk_if}" TNM_NET = "GRPclk_if";
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NET "{clk_fx}" TNM_NET = "GRPclk_fx";
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TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%;
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TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%;
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TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY;
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TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY;
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""", clk_if=clk_if, clk_fx=clk_fx)
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except ContraintError:
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pass
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