25 lines
517 B
Python
25 lines
517 B
Python
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl import verilog
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from migen.genlib.record import *
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L = [
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("position", [
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("x", 10, DIR_M_TO_S),
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("y", 10, DIR_M_TO_S),
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]),
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("color", 32, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M)
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]
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class Test(Module):
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def __init__(self):
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master = Record(L)
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slave = Record(L)
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self.comb += master.connect(slave)
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print(verilog.convert(Test()))
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print(layout_len(L))
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print(layout_partial(L, "position/x", "color"))
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