113 lines
3.0 KiB
Python
113 lines
3.0 KiB
Python
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from migen.fhdl.structure import *
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from migen.bus import dfi
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from migen.bank.description import *
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from migen.bank import csrgen
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def _data_en(trigger, output, delay, duration):
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dcounter = Signal(BV(4))
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dce = Signal()
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return [
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If(trigger,
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dcounter.eq(delay),
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dce.eq(1)
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).Elif(dce,
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dcounter.eq(dcounter - 1),
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If(dcounter == 0,
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If(~output,
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output.eq(1),
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dcounter.eq(duration)
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).Else(
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output.eq(0),
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dce.eq(0)
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)
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)
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)
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]
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class DFIInjector:
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def __init__(self, csr_address, a, ba, d, nphases=1):
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self._int = dfi.Interface(a, ba, d, nphases)
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self.slave = dfi.Interface(a, ba, d, nphases)
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self.master = dfi.Interface(a, ba, d, nphases)
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self._sel = Field("sel")
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self._cke = Field("cke")
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self._control = RegisterFields("control", [self._sel, self._cke])
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self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
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self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
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self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
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self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
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self._rddata = Field("rddata", 1, WRITE_ONLY, READ_ONLY)
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self._wrdata = Field("wrdata", 1, WRITE_ONLY, READ_ONLY)
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self._command = RegisterFields("command",
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[self._cs, self._we, self._cas, self._ras, self._rddata, self._wrdata])
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self._address = RegisterField("address", a)
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self._baddress = RegisterField("baddress", ba)
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self._rddelay = RegisterField("rddelay", 4, reset=5)
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self._rdduration = RegisterField("rdduration", 3, reset=0)
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self._wrdelay = RegisterField("wrdelay", 4, reset=3)
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self._wrduration = RegisterField("wrduration", 3, reset=0)
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self.bank = csrgen.Bank([
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self._control, self._command,
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self._address, self._baddress,
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self._rddelay, self._rdduration,
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self._wrdelay, self._wrduration
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], address=csr_address)
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def get_fragment(self):
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comb = []
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sync = []
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# mux
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connect_int = dfi.interconnect_stmts(self._int, self.master)
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connect_slave = dfi.interconnect_stmts(self.slave, self.master)
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comb.append(If(self._sel.r, *connect_slave).Else(*connect_int))
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# phases
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rddata_en = Signal()
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wrdata_en = Signal()
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for phase in self._int.phases:
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comb += [
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phase.cke.eq(self._cke.r),
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phase.rddata_en.eq(rddata_en),
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phase.wrdata_en.eq(wrdata_en)
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]
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cmdphase = self._int.phases[0]
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for phase in self._int.phases[1:]:
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comb += [
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phase.cs_n.eq(1),
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phase.we_n.eq(1),
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phase.cas_n.eq(1),
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phase.ras_n.eq(1)
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]
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# commands
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comb += [
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If(self._command.re,
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cmdphase.cs_n.eq(~self._cs.r),
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cmdphase.we_n.eq(~self._we.r),
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cmdphase.cas_n.eq(~self._cas.r),
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cmdphase.ras_n.eq(~self._ras.r)
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).Else(
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cmdphase.cs_n.eq(1),
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cmdphase.we_n.eq(1),
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cmdphase.cas_n.eq(1),
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cmdphase.ras_n.eq(1)
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)
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]
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# data enables
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sync += _data_en(self._command.re & self._rddata.r,
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rddata_en,
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self._rddelay.field.r, self._rdduration.field.r)
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sync += _data_en(self._command.re & self._wrdata.r,
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wrdata_en,
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self._wrdelay.field.r, self._wrduration.field.r)
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return Fragment(comb, sync) + self.bank.get_fragment()
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