60 lines
1.9 KiB
ReStructuredText
60 lines
1.9 KiB
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.. _about:
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================
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About LiteEth
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================
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LiteEth provides a small footprint and configurable Ethernet core.
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LiteEth is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA IP cores by providing simple, elegant and efficient implementations
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ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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LiteEth uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteEth can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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.. _about-toolchain:
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Features
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========
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- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
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- Hardware UDP/IP stack with ARP and ICMP
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Possibles improvements
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======================
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- add standardized interfaces (AXI, Avalon-ST)
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- add DMA interface to MAC
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- add hardware Etherbone support
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- add RGMII/SGMII PHYs
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- ... See below Support and Consulting :)
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Support and Consulting
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======================
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We love open-source hardware and like sharing our designs with others.
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LiteEth is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteEth or if you are already a happy user
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and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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Contact
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=======
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E-mail: florent [AT] enjoy-digital.fr
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