44 lines
1.3 KiB
Python
44 lines
1.3 KiB
Python
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from liteeth.common import *
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from liteeth.generic import *
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class LiteEthIPV4Checksum(Module):
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def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
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self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
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self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
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self.header = Signal(ipv4_header_len*8)
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self.value = Signal(16)
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self.done = Signal()
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###
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s = Signal(17)
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r = Signal(17)
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n_cycles = 0
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for i in range(ipv4_header_len//2):
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if skip_checksum and (i == ipv4_header["checksum"].byte//2):
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pass
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else:
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s_next = Signal(17)
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r_next = Signal(17)
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self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
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r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
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if (i%words_per_clock_cycle) != 0:
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self.comb += r_next_eq
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else:
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self.sync += \
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If(self.reset,
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r_next.eq(0)
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).Elif(self.ce & ~self.done,
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r_next_eq
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)
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n_cycles += 1
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s, r = s_next, r_next
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self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
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if not skip_checksum:
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n_cycles += 1
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self.submodules.counter = counter = Counter(max=n_cycles+1)
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self.comb += [
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counter.reset.eq(self.reset),
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counter.ce.eq(self.ce & ~self.done),
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self.done.eq(counter.value == n_cycles)
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]
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