50 lines
762 B
Python
50 lines
762 B
Python
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from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from miscope.storage import RunLengthEncoder
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rle_test_seq = iter(
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[ 0x00AA,
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0x00AB,
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0x00AC,
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0x00AC,
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0x00AC,
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0x00AC,
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0x00AD,
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0x00AE,
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0x00AE,
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0x00AE,
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0x00AE,
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0x00AE,
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0x00AE,
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0x00AE,
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0x00AE
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]*10
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)
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class TB(Module):
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def __init__(self):
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# Rle
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self.submodules.rle = RunLengthEncoder(16, 32)
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def do_simulation(self, s):
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s.wr(self.rle._r_enable.storage, 1)
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s.wr(self.rle.sink.stb, 1)
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try:
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s.wr(self.rle.sink.dat, next(rle_test_seq))
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except:
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pass
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def main():
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tb = TB()
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sim = Simulator(tb, TopLevel("tb_rle.vcd"))
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sim.run(2000)
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print("Sim Done")
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input()
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main()
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