litex/misoclib/com/liteeth/doc/source/home_page_layout.html

<img alt="./_static/LiteEth_logo_full.png" src="_static/LiteEth_logo_full.png">

<h3>A small footprint and configurable Ethernet core with UDP/IP hw stack and Etherbone frontend</b>.</h3>

<div class="container" style="width:100%;margin-bottom:10px;">

	<div class="one-third-container" style="width:32%; display:inline-block;">
		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
			<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteEth footprint is really small!</p></div>
		</div>
	</div>
	<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
			<div class="signpost-body" style=""><p>LiteEth generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Implement only the layers you need, store data in RAM or DMA, use full-hardware UDP/IP stack and so on...)</p></div>
		</div>
	</div>
	<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
			<div class="signpost-body" style=""><p>LiteEth can target all FPGAs regardless of the vendor, you only have to ensure that your PHY is available!</p></div>
		</div>
	</div>
</div>