litex/misoclib/mem/litesata/phy/__init__.py

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from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy.ctrl import *
from misoclib.mem.litesata.phy.datapath import *
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class LiteSATAPHY(Module):
def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq):
self.clock_pads = clock_pads_or_refclk
self.pads = pads
self.revision = revision
# Transceiver / Clocks
if device[:3] == "xc7": # Kintex 7
from misoclib.mem.litesata.phy.k7.trx import K7LiteSATAPHYTRX
from misoclib.mem.litesata.phy.k7.crg import K7LiteSATAPHYCRG
self.submodules.trx = K7LiteSATAPHYTRX(pads, revision)
self.submodules.crg = K7LiteSATAPHYCRG(clock_pads_or_refclk, pads, self.trx, revision, clk_freq)
else:
raise NotImplementedError
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# Control
self.submodules.ctrl = LiteSATAPHYCtrl(self.trx, self.crg, clk_freq)
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# Datapath
self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl)
self.sink, self.source = self.datapath.sink, self.datapath.source