litex/misoclib/identifier/__init__.py

from migen.fhdl.std import *
from migen.bank.description import *

from misoclib.identifier import git

class Identifier(Module, AutoCSR):
	def __init__(self, sysid, frequency, revision=None):
		self._sysid = CSRStatus(16)
		self._revision = CSRStatus(32)
		self._frequency = CSRStatus(32)

		###

		if revision is None:
			revision = git.get_id()

		self.comb += [
			self._sysid.status.eq(sysid),
			self._revision.status.eq(revision),
			self._frequency.status.eq(frequency)
		]
Use migen.fhdl.std 2013-05-22 11:10:13 -04:00			`from migen.fhdl.std import *`
Identifier 2012-05-16 19:41:41 -04:00			`from migen.bank.description import *`

use git commit id as version 2013-11-09 10:38:44 -05:00			`from misoclib.identifier import git`
Identifier 2012-05-16 19:41:41 -04:00
Convert to new CSR API 2013-03-30 12:28:15 -04:00			`class Identifier(Module, AutoCSR):`
use cachesize reported in wishbone2lasmi 2015-02-27 08:13:38 -05:00			`def __init__(self, sysid, frequency, revision=None):`
replace self._r_register by self._register in all CSR declaration 2015-02-27 04:36:09 -05:00			`self._sysid = CSRStatus(16)`
			`self._revision = CSRStatus(32)`
			`self._frequency = CSRStatus(32)`
remove trailing whitespaces 2014-10-17 05:14:35 -04:00
Use new module, autoreg and eventmanager Migen APIs 2013-03-10 14:32:38 -04:00			`###`

use git commit id as version 2013-11-09 10:38:44 -05:00			`if revision is None:`
			`revision = git.get_id()`

Use new module, autoreg and eventmanager Migen APIs 2013-03-10 14:32:38 -04:00			`self.comb += [`
replace self._r_register by self._register in all CSR declaration 2015-02-27 04:36:09 -05:00			`self._sysid.status.eq(sysid),`
			`self._revision.status.eq(revision),`
use cachesize reported in wishbone2lasmi 2015-02-27 08:13:38 -05:00			`self._frequency.status.eq(frequency)`
Identifier 2012-05-16 19:41:41 -04:00			`]`