2013-07-15 11:45:55 -04:00
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from migen.fhdl.std import *
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2014-01-28 07:50:01 -05:00
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from migen.sim.generic import run_simulation
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2013-07-15 11:45:55 -04:00
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2015-02-27 10:55:27 -05:00
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from misoclib.sdram.bus import lasmibus
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2014-11-26 04:37:50 -05:00
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from misoclib.sdram.lasmicon import *
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2013-07-15 11:45:55 -04:00
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from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
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def my_generator_r(n):
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for x in range(10):
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t = TRead(128*n + 48*n*x)
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yield t
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print("{0:3}: reads done".format(n))
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def my_generator_w(n):
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for x in range(10):
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t = TWrite(128*n + 48*n*x, x)
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yield t
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print("{0:3}: writes done".format(n))
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def my_generator(n):
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if n % 2:
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return my_generator_w(n // 2)
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else:
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return my_generator_r(n // 2)
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class TB(Module):
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def __init__(self):
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self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
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2013-11-23 11:51:41 -05:00
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self.submodules.xbar = lasmibus.Crossbar([self.dut.lasmic], self.dut.nrowbits)
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2013-07-15 11:45:55 -04:00
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self.submodules.logger = DFILogger(self.dut.dfi)
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2013-11-23 11:51:41 -05:00
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masters = [self.xbar.get_master() for i in range(6)]
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2013-07-15 11:45:55 -04:00
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self.initiators = [Initiator(my_generator(n), master)
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2013-11-23 11:51:41 -05:00
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for n, master in enumerate(masters)]
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2013-07-15 11:45:55 -04:00
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self.submodules += self.initiators
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2014-01-28 07:50:01 -05:00
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if __name__ == "__main__":
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run_simulation(TB(), vcd_name="my.vcd")
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