2013-02-22 08:28:05 -05:00
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from migen.fhdl.structure import *
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2013-09-21 07:04:07 -04:00
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from migen.flow.actor import *
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from migen.flow.network import *
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2013-02-22 08:28:05 -05:00
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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2013-09-22 12:41:44 -04:00
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from miscope.std import *
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2013-09-22 07:28:12 -04:00
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from miscope.trigger import Trigger
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2014-04-18 04:33:05 -04:00
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from miscope.storage import Recorder, RunLengthEncoder
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2013-09-22 07:28:12 -04:00
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2013-09-21 07:04:07 -04:00
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class MiLa(Module, AutoCSR):
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2013-09-22 12:41:44 -04:00
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def __init__(self, width, depth, ports, rle=False):
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2013-09-22 07:28:12 -04:00
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self.width = width
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2013-09-22 12:41:44 -04:00
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self.sink = rec_dat(width)
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2013-09-22 07:28:12 -04:00
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trigger = Trigger(width, ports)
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recorder = Recorder(width, depth)
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self.submodules.trigger = trigger
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self.submodules.recorder = recorder
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2013-03-21 07:23:44 -04:00
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2013-09-22 12:41:44 -04:00
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self.comb += [
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trigger.sink.stb.eq(self.sink.stb),
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trigger.sink.dat.eq(self.sink.dat),
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recorder.trig_sink.stb.eq(trigger.source.stb),
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recorder.trig_sink.hit.eq(trigger.source.hit),
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trigger.source.ack.eq(recorder.trig_sink.ack),
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self.sink.ack.eq(1), #FIXME
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2013-02-22 08:28:05 -05:00
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]
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2013-09-21 07:04:07 -04:00
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2013-09-22 12:41:44 -04:00
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if rle:
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self.submodules.rle = RunLengthEncoder(width, 1024)
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self.comb +=[
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self.rle.sink.stb.eq(self.sink.stb),
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self.rle.sink.dat.eq(self.sink.dat),
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recorder.dat_sink.stb.eq(self.rle.source.stb),
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recorder.dat_sink.dat.eq(self.rle.source.dat),
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]
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else:
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self.comb +=[
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recorder.dat_sink.stb.eq(self.sink.stb),
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recorder.dat_sink.dat.eq(self.sink.dat),
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]
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