litex/sim/tb_rle.py

46 lines
669 B
Python
Raw Normal View History

2013-09-22 12:41:44 -04:00
from migen.fhdl.std import *
2014-04-18 04:33:05 -04:00
from migen.sim.generic import run_simulation
2013-09-22 12:41:44 -04:00
2014-04-18 04:33:05 -04:00
from miscope import storage
2013-09-22 12:41:44 -04:00
rle_test_seq = iter(
[ 0x00AA,
0x00AB,
0x00AC,
0x00AC,
0x00AC,
0x00AC,
0x00AD,
0x00AE,
0x00AE,
0x00AE,
0x00AE,
0x00AE,
0x00AE,
0x00AE,
0x00AE
]*10
)
class TB(Module):
def __init__(self):
# Rle
2014-04-18 04:33:05 -04:00
self.submodules.rle = storage.RunLengthEncoder(16, 32)
2013-09-22 12:41:44 -04:00
2014-04-18 04:33:05 -04:00
def do_simulation(self, selfp):
selfp.rle._r_enable.storage = 1
selfp.rle.sink.stb = 1
2013-09-22 12:41:44 -04:00
try:
2014-04-18 04:33:05 -04:00
selfp.rle.sink.dat = next(rle_test_seq)
2013-09-22 12:41:44 -04:00
except:
pass
def main():
tb = TB()
2014-04-18 04:33:05 -04:00
run_simulation(tb, ncycles=8000, vcd_name="tb_rle.vcd")
2013-09-22 12:41:44 -04:00
print("Sim Done")
input()
main()