2014-04-18 04:33:05 -04:00
|
|
|
import string
|
|
|
|
import serial
|
|
|
|
from struct import *
|
|
|
|
from migen.fhdl.structure import *
|
|
|
|
from miscope.host.regs import *
|
|
|
|
|
|
|
|
def write_b(uart, data):
|
|
|
|
uart.write(pack('B',data))
|
|
|
|
|
|
|
|
class Uart2Wishbone:
|
|
|
|
WRITE_CMD = 0x01
|
|
|
|
READ_CMD = 0x02
|
2014-06-26 05:09:59 -04:00
|
|
|
def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
|
2014-04-18 04:33:05 -04:00
|
|
|
self.port = port
|
2014-06-05 08:43:29 -04:00
|
|
|
self.baudrate = str(baudrate)
|
2014-04-18 04:33:05 -04:00
|
|
|
self.debug = debug
|
|
|
|
self.uart = serial.Serial(port, baudrate, timeout=0.25)
|
2014-06-26 05:09:59 -04:00
|
|
|
self.regs = build_map(addrmap, busword, self.read, self.write)
|
2014-04-18 04:33:05 -04:00
|
|
|
|
|
|
|
def open(self):
|
|
|
|
self.uart.flushOutput()
|
|
|
|
self.uart.close()
|
|
|
|
self.uart.open()
|
|
|
|
self.uart.flushInput()
|
2014-05-20 07:16:24 -04:00
|
|
|
try:
|
2014-05-22 10:11:32 -04:00
|
|
|
self.regs.uart2wb_sel.write(1)
|
2014-05-20 07:16:24 -04:00
|
|
|
except:
|
|
|
|
pass
|
2014-08-03 02:38:37 -04:00
|
|
|
|
2014-04-18 04:33:05 -04:00
|
|
|
def close(self):
|
2014-05-20 07:16:24 -04:00
|
|
|
try:
|
2014-05-22 10:11:32 -04:00
|
|
|
self.regs.uart2wb_sel.write(0)
|
2014-05-20 07:16:24 -04:00
|
|
|
except:
|
|
|
|
pass
|
2014-08-03 06:26:41 -04:00
|
|
|
self.uart.flushOutput()
|
2014-04-18 04:33:05 -04:00
|
|
|
self.uart.close()
|
|
|
|
|
|
|
|
def read(self, addr, burst_length=1):
|
|
|
|
self.uart.flushInput()
|
|
|
|
write_b(self.uart, self.READ_CMD)
|
|
|
|
write_b(self.uart, burst_length)
|
|
|
|
addr = addr//4
|
|
|
|
write_b(self.uart, (addr & 0xff000000) >> 24)
|
|
|
|
write_b(self.uart, (addr & 0x00ff0000) >> 16)
|
|
|
|
write_b(self.uart, (addr & 0x0000ff00) >> 8)
|
|
|
|
write_b(self.uart, (addr & 0x000000ff))
|
|
|
|
values = []
|
|
|
|
for i in range(burst_length):
|
|
|
|
val = 0
|
|
|
|
for j in range(4):
|
|
|
|
val = val << 8
|
|
|
|
val |= ord(self.uart.read())
|
|
|
|
if self.debug:
|
|
|
|
print("RD %08X @ %08X" %(val, (addr+i)*4))
|
|
|
|
values.append(val)
|
|
|
|
if burst_length == 1:
|
|
|
|
return values[0]
|
|
|
|
else:
|
|
|
|
return values
|
|
|
|
|
|
|
|
def write(self, addr, data):
|
|
|
|
if isinstance(data, list):
|
|
|
|
burst_length = len(data)
|
|
|
|
else:
|
|
|
|
burst_length = 1
|
|
|
|
write_b(self.uart, self.WRITE_CMD)
|
|
|
|
write_b(self.uart, burst_length)
|
|
|
|
addr = addr//4
|
|
|
|
write_b(self.uart, (addr & 0xff000000) >> 24)
|
|
|
|
write_b(self.uart, (addr & 0x00ff0000) >> 16)
|
|
|
|
write_b(self.uart, (addr & 0x0000ff00) >> 8)
|
|
|
|
write_b(self.uart, (addr & 0x000000ff))
|
|
|
|
if isinstance(data, list):
|
|
|
|
for i in range(len(data)):
|
|
|
|
dat = data[i]
|
|
|
|
for j in range(4):
|
|
|
|
write_b(self.uart, (dat & 0xff000000) >> 24)
|
|
|
|
dat = dat << 8
|
|
|
|
if self.debug:
|
|
|
|
print("WR %08X @ %08X" %(data[i], (addr + i)*4))
|
|
|
|
else:
|
|
|
|
dat = data
|
|
|
|
for j in range(4):
|
|
|
|
write_b(self.uart, (dat & 0xff000000) >> 24)
|
|
|
|
dat = dat << 8
|
|
|
|
if self.debug:
|
|
|
|
print("WR %08X @ %08X" %(data, (addr * 4)))
|