81 lines
2.0 KiB
Tcl
81 lines
2.0 KiB
Tcl
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# Set the option CHECK_SYNTHESIS to 1 if you want to have -check_synthesis in simulation. For now
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# tools like Modelsim generate too many false positives so it is disabled by default:
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set CHECK_SYNTHESIS 0
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set NO_DEBUG 0
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set HDL_TOOLTYPE SIMULATION
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set HDL_TOOLNAME modelsim
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set HDL_PUTS echo
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set HDL_MSG_FORMAT "********** %s **********"
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# Return the directory containing library lib
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proc getvmap {lib} {
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if {[catch {vmap $lib} result]} {
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# Library does not exist yet => default directory
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return $lib
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}
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set dir ""
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# Get directory returned by vmap
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regexp { maps to directory (.*)\.$} $result match dir
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return $dir
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}
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proc hdl_tool_library {lib} {
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set lib [string tolower $lib]
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# Delete library
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set path [getvmap $lib]
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if {[file isdirectory $path]} {
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catch {
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vdel -lib $path -all
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}
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}
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# Create library
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set path [get_lib_path]/$lib
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vlib $path
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vmap $lib $path
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}
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proc hdl_tool_compile {format version incdirs library define files behavioral} {
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global CHECK_SYNTHESIS
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global NO_DEBUG
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switch $format {
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"vhdl" {
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set command vcom
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if { $version == 87 } {
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lappend command -87
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} elseif { $version == 93 } {
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lappend command -93
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}
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# More strict for synthesizable modules
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if { ! $behavioral && $CHECK_SYNTHESIS } {
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lappend command -check_synthesis
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}
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}
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"verilog" {
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set command vlog
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if {$version == "sv"} {
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lappend command -sv
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}
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lappend command -timescale "1ns/1ns"
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foreach d $define {
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lappend command +define+$d
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}
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foreach i $incdirs {
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lappend command +incdir+$i
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}
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}
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}
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if {$NO_DEBUG} {
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lappend command -nodebug
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}
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lappend command -work [string tolower $library]
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lappend command -quiet
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foreach f $files {
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lappend command $f
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}
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puts -nonewline [eval $command]
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return
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}
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