92 lines
1.9 KiB
Python
92 lines
1.9 KiB
Python
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from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.common import *
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class SATABIST(Module):
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def __init__(self, sector_size=512, max_count=1):
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self.sink = sink = Sink(command_rx_description(32))
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self.source = source = Source(command_tx_description(32))
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self.start = Signal()
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self.sector = Signal(48)
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self.done = Signal()
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self.errors = Signal(32)
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errors = Signal(32)
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inc_errors = Signal()
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self.sync += \
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If(self.start,
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errors.eq(0),
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).Elif(inc_errors,
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errors.eq(errors+1)
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)
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self.comb += self.errors.eq(errors)
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cnt = Signal(32)
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inc_cnt = Signal()
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clr_cnt = Signal()
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self.sync += \
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If(clr_cnt,
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cnt.eq(0),
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).Elif(inc_cnt,
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cnt.eq(cnt+1)
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)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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self.done.eq(1),
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clr_cnt.eq(1),
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If(self.start,
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq((cnt==0)),
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source.eop.eq((cnt==(sector_size*max_count)//4-1)),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(max_count),
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source.data.eq(cnt), #XXX use LFSR
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inc_cnt.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("WAIT_WRITE_ACK")
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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sink.ack.eq(1),
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If(sink.stb & sink.write,
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NextState("SEND_READ_CMD")
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)
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)
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fsm.act("SEND_READ_CMD",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(max_count),
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If(source.ack,
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NextState("WAIT_READ_ACK")
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)
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)
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fsm.act("WAIT_READ_ACK",
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clr_cnt.eq(1),
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If(sink.stb & sink.read,
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NextState("RECEIVE_READ_DATA")
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)
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)
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fsm.act("RECEIVE_READ_DATA",
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sink.ack.eq(1),
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inc_cnt.eq(sink.stb),
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If(sink.stb & (sink.data != cnt), #XXX use LFSR
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inc_errors.eq(1)
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),
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If(sink.stb & sink.eop,
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NextState("IDLE")
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)
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)
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