2015-09-07 18:58:03 -04:00
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from misoclib.com.liteethmini.common import *
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from misoclib.com.liteethmini.generic import *
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2015-01-27 17:59:06 -05:00
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2015-04-13 04:20:02 -04:00
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2015-01-28 03:14:01 -05:00
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class LiteEthPHYLoopbackCRG(Module, AutoCSR):
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2015-04-13 03:53:43 -04:00
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def __init__(self):
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self._reset = CSRStorage()
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2015-04-13 05:23:27 -04:00
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# # #
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2015-04-13 03:53:43 -04:00
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal())
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]
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2015-01-27 17:59:06 -05:00
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2015-04-13 03:53:43 -04:00
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reset = self._reset.storage
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self.comb += [
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self.cd_eth_rx.rst.eq(reset),
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self.cd_eth_tx.rst.eq(reset)
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]
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2015-01-27 17:59:06 -05:00
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2015-04-13 04:20:02 -04:00
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2015-01-28 03:14:01 -05:00
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class LiteEthPHYLoopback(Module, AutoCSR):
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2015-04-13 03:53:43 -04:00
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def __init__(self):
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self.dw = 8
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self.submodules.crg = LiteEthLoopbackPHYCRG()
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self.sink = sink = Sink(eth_phy_description(8))
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self.source = source = Source(eth_phy_description(8))
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self.comb += Record.connect(self.sink, self.source)
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