2013-05-22 11:10:13 -04:00
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from migen.fhdl.std import *
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2011-12-13 11:33:12 -05:00
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from migen.bus import wishbone
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2013-02-24 06:31:00 -05:00
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from migen.genlib.misc import timeline
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2011-12-13 11:33:12 -05:00
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2013-03-10 14:32:38 -04:00
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class NorFlash(Module):
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2013-03-26 12:57:17 -04:00
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def __init__(self, pads, rd_timing):
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2012-02-15 10:55:13 -05:00
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self.bus = wishbone.Interface()
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2011-12-13 11:33:12 -05:00
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2013-03-10 14:32:38 -04:00
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###
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2013-03-26 12:57:17 -04:00
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2013-05-22 11:10:13 -04:00
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adr_width = flen(pads.adr) + 1
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2013-03-26 12:57:17 -04:00
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self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1),
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pads.ce_n.eq(0)]
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2013-03-10 14:32:38 -04:00
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self.sync += timeline(self.bus.cyc & self.bus.stb, [
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2013-03-26 12:57:17 -04:00
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(0, [pads.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
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2013-03-10 14:32:38 -04:00
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(rd_timing, [
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2013-03-26 12:57:17 -04:00
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self.bus.dat_r[16:].eq(pads.d),
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pads.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
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2013-03-10 14:32:38 -04:00
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(2*rd_timing, [
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2013-03-26 12:57:17 -04:00
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self.bus.dat_r[:16].eq(pads.d),
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2012-03-15 15:26:04 -04:00
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self.bus.ack.eq(1)]),
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2013-03-10 14:32:38 -04:00
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(2*rd_timing + 1, [
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2012-03-15 15:26:04 -04:00
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self.bus.ack.eq(0)])
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])
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