62 lines
1.9 KiB
Python
62 lines
1.9 KiB
Python
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from migen.fhdl.std import *
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from migen.actorlib.crc import *
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from misoclib.ethmac.std import *
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from misoclib.ethmac.test import *
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frame_data = [
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0x00, 0x0A, 0xE6, 0xF0, 0x05, 0xA3, 0x00, 0x12,
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0x34, 0x56, 0x78, 0x90, 0x08, 0x00, 0x45, 0x00,
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0x00, 0x30, 0xB3, 0xFE, 0x00, 0x00, 0x80, 0x11,
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0x72, 0xBA, 0x0A, 0x00, 0x00, 0x03, 0x0A, 0x00,
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0x00, 0x02, 0x04, 0x00, 0x04, 0x00, 0x00, 0x1C,
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0x89, 0x4D, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
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0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13
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]
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frame_crc = [
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0x7A, 0xD5, 0x6B, 0xB3
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]
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class TB(Module):
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def __init__(self):
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sm = self.submodules
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# Streamer (DATA) --> CRC32Inserter --> Logger (expect DATA + CRC)
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sm.inserter_streamer = PacketStreamer(frame_data)
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sm.crc32_inserter = CRC32Inserter(eth_description(8))
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sm.inserter_logger = PacketLogger()
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self.comb +=[
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self.inserter_streamer.source.connect(self.crc32_inserter.sink),
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self.crc32_inserter.source.connect(self.inserter_logger.sink),
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]
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# Streamer (DATA + CRC) --> CRC32Checher --> Logger (except DATA + CRC + check)
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sm.checker_streamer = PacketStreamer(frame_data+frame_crc)
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sm.crc32_checker = CRC32Checker(eth_description(8))
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sm.checker_logger = PacketLogger()
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self.comb +=[
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self.checker_streamer.source.connect(self.crc32_checker.sink),
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self.crc32_checker.source.connect(self.checker_logger.sink),
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]
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def gen_simulation(self, selfp):
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for i in range(500):
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yield
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inserter_reference = frame_data + frame_crc
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inserter_generated = self.inserter_logger.data
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checker_reference = frame_data
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checker_generated = self.checker_logger.data
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print_results("inserter", inserter_reference, inserter_generated)
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print_results("checker", checker_reference, checker_generated)
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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