litex/examples/basic/arrays.py

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from migen import *
from migen.fhdl import verilog
2015-04-13 14:45:35 -04:00
2013-03-12 11:45:28 -04:00
class Example(Module):
def __init__(self):
dx = 2
dy = 2
x = Signal(max=dx)
y = Signal(max=dy)
out = Signal()
my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
self.comb += out.eq(my_2d_array[x][y])
we = Signal()
inp = Signal()
self.sync += If(we,
my_2d_array[x][y].eq(inp)
)
ina = Array(Signal() for a in range(dx))
outa = Array(Signal() for a in range(dy))
self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
if __name__ == "__main__":
print(verilog.convert(Example()))