2013-03-25 09:42:48 -04:00
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#ifndef __HW_FLAGS_H
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#define __HW_FLAGS_H
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#define UART_EV_TX 0x1
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#define UART_EV_RX 0x2
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2014-08-08 09:56:35 -04:00
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#define DFII_CONTROL_SEL 0x01
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#define DFII_CONTROL_CKE 0x02
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#define DFII_CONTROL_ODT 0x04
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#define DFII_CONTROL_RESET_N 0x08
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2013-03-25 09:42:48 -04:00
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#define DFII_COMMAND_CS 0x01
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#define DFII_COMMAND_WE 0x02
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#define DFII_COMMAND_CAS 0x04
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#define DFII_COMMAND_RAS 0x08
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#define DFII_COMMAND_WRDATA 0x10
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#define DFII_COMMAND_RDDATA 0x20
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2014-11-20 19:47:11 -05:00
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#define ETHMAC_EV_SRAM_WRITER 0x1
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#define ETHMAC_EV_SRAM_READER 0x1
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2013-03-25 09:42:48 -04:00
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2013-03-28 14:07:17 -04:00
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#define CLKGEN_STATUS_BUSY 0x1
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#define CLKGEN_STATUS_PROGDONE 0x2
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#define CLKGEN_STATUS_LOCKED 0x4
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2013-04-14 10:33:00 -04:00
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#define DVISAMPLER_TOO_LATE 0x1
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#define DVISAMPLER_TOO_EARLY 0x2
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2013-09-14 11:14:20 -04:00
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#define DVISAMPLER_DELAY_MASTER_CAL 0x01
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#define DVISAMPLER_DELAY_MASTER_RST 0x02
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#define DVISAMPLER_DELAY_SLAVE_CAL 0x04
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#define DVISAMPLER_DELAY_SLAVE_RST 0x08
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#define DVISAMPLER_DELAY_INC 0x10
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#define DVISAMPLER_DELAY_DEC 0x20
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2013-04-14 10:33:00 -04:00
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2013-05-09 04:52:43 -04:00
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#define DVISAMPLER_SLOT_EMPTY 0
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#define DVISAMPLER_SLOT_LOADED 1
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#define DVISAMPLER_SLOT_PENDING 2
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2013-03-25 09:42:48 -04:00
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#endif /* __HW_FLAGS_H */
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