2014-06-07 06:24:19 -04:00
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from migen.fhdl.std import *
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class CRG_DS(Module):
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2014-06-20 11:10:09 -04:00
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def __init__(self, platform, clk_name, rst_name, rst_invert=False):
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2014-06-07 06:24:19 -04:00
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reset_less = rst_name is None
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self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
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self._clk = platform.request(clk_name)
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self.specials += Instance("IBUFGDS",
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Instance.Input("I", self._clk.p),
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Instance.Input("IB", self._clk.n),
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Instance.Output("O", self.cd_sys.clk)
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)
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if not reset_less:
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if rst_invert:
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self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
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else:
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self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
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