110 lines
2.6 KiB
Python
110 lines
2.6 KiB
Python
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from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.bus import csr
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from miscope.triggering import *
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from miscope.std.truthtable import *
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from miscope.std import cif
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from mibuild.tools import write_to_file
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try:
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from csr_header import *
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print("csr_header imported")
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except:
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print("csr_header not found")
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class Csr2Trans():
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def __init__(self):
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self.t = []
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def write_csr(self, adr, value):
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self.t.append(TWrite(adr//4, value))
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def read_csr(self, adr):
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self.t.append(TRead(adr//4))
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def csr_prog_mila():
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bus = Csr2Trans()
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trigger_port0_mask_write(bus, 0xFFFFFFFF)
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trigger_port0_trig_write(bus, 0xDEADBEEF)
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trigger_port1_mask_write(bus, 0xFFFFFFFF)
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trigger_port1_trig_write(bus, 0xDEADBEEF)
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trigger_port1_mask_write(bus, 0xFFFFFFFF)
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trigger_port1_mask_write(bus, 0xFFFFFFFF)
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trigger_port1_trig_write(bus, 0xDEADBEEF)
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sum_tt = gen_truth_table("i1 & i2 & i3 & i4")
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sum_trans = []
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for i in range(len(sum_tt)):
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trigger_sum_prog_adr_write(bus, i)
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trigger_sum_prog_dat_write(bus, sum_tt[i])
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trigger_sum_prog_we_write(bus, 1)
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return bus.t
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csr_done = False
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def csr_transactions():
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for t in csr_prog_mila():
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yield t
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global csr_done
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csr_done = True
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for t in range(100):
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yield None
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class TB(Module):
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csr_base = 0
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csr_map = {
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"trigger": 1,
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}
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def __init__(self, first_run=False):
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# Csr Master
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if not first_run:
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self.submodules.master = csr.Initiator(csr_transactions())
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# Trigger
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term0 = Term(32)
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term1 = Term(32)
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term2 = Term(32)
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term3 = Term(32)
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self.submodules.trigger = Trigger(32, [term0, term1, term2, term3])
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# Csr
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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if not first_run:
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self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
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self.terms = [term0, term1, term2, term3]
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def do_simulation(self, s):
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for term in self.terms:
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s.wr(term.sink.stb, 1)
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if csr_done:
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s.wr(self.terms[0].sink.payload.d, 0xDEADBEEF)
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s.wr(self.terms[1].sink.payload.d ,0xCAFEFADE)
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s.wr(self.terms[2].sink.payload.d, 0xDEADBEEF)
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s.wr(self.terms[3].sink.payload.d, 0xCAFEFADE)
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s.interrupt = self.master.done
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def main():
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tb = TB(first_run=True)
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csr_py_header = cif.get_py_csr_header(tb.csr_base, tb.csrbankarray)
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write_to_file("csr_header.py", csr_py_header)
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tb = TB()
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sim = Simulator(tb, TopLevel("tb_trigger_csr.vcd"))
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sim.run(2000)
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print("Sim Done")
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input()
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main()
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