2015-11-07 06:26:46 -05:00
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[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
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path = litex/soc/cores/cpu/lm32/verilog/submodule
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url = https://github.com/m-labs/lm32.git
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[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
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path = litex/soc/cores/cpu/mor1kx/verilog
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url = https://github.com/openrisc/mor1kx.git
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[submodule "litex/soc/software/compiler_rt"]
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path = litex/soc/software/compiler_rt
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url = http://llvm.org/git/compiler-rt.git
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2016-03-31 18:09:17 -04:00
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[submodule "litex/soc/cores/cpu/picorv32/verilog"]
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path = litex/soc/cores/cpu/picorv32/verilog
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url = https://github.com/cliffordwolf/picorv32
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