litex/software/bios/sdram.h

#ifndef __SDRAM_H
#define __SDRAM_H

#include <generated/csr.h>

void sdrsw(void);
void sdrhw(void);
void sdrrow(char *_row);
void sdrrdbuf(int dq);
void sdrrd(char *startaddr, char *dq);
void sdrrderr(char *count);
void sdrwr(char *startaddr);

#ifdef CSR_DDRPHY_BASE
void sdrwlon(void);
void sdrwloff(void);
int sdrlevel(void);
#endif

unsigned int seed_to_data(unsigned int seed, int random);
int memtest_silent(void);
int memtest(void);
int sdrinit(void);

#endif /* __SDRAM_H */
bios: asmiprobe command Because with reordering architectures come order-dependent intermittent bugs. 2012-08-04 10:32:15 -04:00			`#ifndef __SDRAM_H`
			`#define __SDRAM_H`
bios: DDR initialization skeleton 2012-02-17 12:47:04 -05:00
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 02:25:26 -04:00			`#include <generated/csr.h>`

bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM 2014-05-23 15:31:26 -04:00			`void sdrsw(void);`
			`void sdrhw(void);`
			`void sdrrow(char *_row);`
bios: add DQ filtering to sdrrd, add sdrrdbuf command 2014-09-01 02:58:58 -04:00			`void sdrrdbuf(int dq);`
			`void sdrrd(char startaddr, char dq);`
bios: add sdrrderr 2014-09-01 03:23:37 -04:00			`void sdrrderr(char *count);`
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM 2014-05-23 15:31:26 -04:00			`void sdrwr(char *startaddr);`
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 02:25:26 -04:00
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 06:25:59 -05:00			`#ifdef CSR_DDRPHY_BASE`
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 02:25:26 -04:00			`void sdrwlon(void);`
			`void sdrwloff(void);`
			`int sdrlevel(void);`
			`#endif`

software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter) 2015-03-26 17:16:31 -04:00			`unsigned int seed_to_data(unsigned int seed, int random);`
bios: automatically enable hardware memory controller and test memory 2012-05-15 13:29:26 -04:00			`int memtest_silent(void);`
bios: print number of memory errors 2013-02-24 10:51:03 -05:00			`int memtest(void);`
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM 2014-05-23 15:31:26 -04:00			`int sdrinit(void);`
bios: DDR initialization skeleton 2012-02-17 12:47:04 -05:00
bios: asmiprobe command Because with reordering architectures come order-dependent intermittent bugs. 2012-08-04 10:32:15 -04:00			`#endif /* __SDRAM_H */`